View CXP87532_1017881.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXP87532/87540
CMOS 8-bit Single Chip Microcomputer
Description The CXP87532/87540 is a CMOS 8-bit microcomputer which consists of arithmetic coprocessor, A/D converter, serial interface, timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit, PWM generator and the measuring circuit which measures signals of capstan FG, drum FG/PG, reel FG and other servo systems, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also this IC provides power on reset function, sleep/stop function which enables to lower power consumption. 100 pin QFP (Plastic) 100 pin LQFP (Plastic)
Structure Silicon gate CMOS IC
Features * A wide instruction set (213 instructions) which covers various types of data -- 16-bit operation multiplycation and division/boolean bit operation instructions * Minimum instruction cycle During operation 326ns/12.288MHz * Incorporated ROM capacity 32K bytes (CXP87532) 40K bytes (CXP87540) * Incorporated RAM capacity 1344 bytes * Peripheral functions -- Arithmetic coprocessor Multiplying with code, sum of products with code, high speed execution of many bits shift rotation operation -- A/D converter 8-bit, 8-channel, successive approximation system (Conversion time 13s/12.288MHz) Incorporated 3-stage FIFO for A/D conversion data -- Serial interface Incorporated buffer RAM for data (1 to 128 bytes auto transfer) 2-channel -- Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer -- High precision timing pattern generator PPG (11 pins) 32-stage programmable -- PWM output 12-bit, 2-channel (Repeated frequency 48kHz) 8-bit, 3-channel (Repeated frequency 48kHz) -- Servo input control Capstan FG, Drum FG/PG, Reel FG input -- FRC capture unit Incorporated 28-bit and 8-stage FIFO * Interruption 12 factors, 12 vectors, multi-interruption possible * Standby mode Sleep/stop * Package 100-pin plastic QFP/LQFP * Piggyback/Evaluation CXP87500 100-pin ceramic QFP/LQFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E93820A81-PS
Block Diagram
EXTAL XTAL RST MP VDD VSS
PE5/PWM3 PE6/PWM4
12BIT PWM GENERATOR 2CH CO-PROCESSOR
PORT C PORT B
SPC700 CPU CORE
CLOCK GENERATOR/ SYSTEM CONTROL
PORT A
PE2/PWM0 PE3/PWM1 PE4/PWM2
8BIT PWM GENERATOR 3CH
PE0/INT0 PE3/INT1 PE1/INT2 NM1
PA0 to PA7
PB0 to PB7
8 FIFO RAM 1344 BYTES PROM 32K/40K BYTES
A/D CONVERTER
INTERRUPT CONTROLLER
PF0/AN0 to PF7/AN7 AVDD AVREF AVSS
PC0 to PC7
PA4/ATFS1 PA5/ATFS3 PA7/ATFS2 PK0/RFDT PK1/MCLK
PORT D
ATF SYNC UNIT
PD0 to PD7
PORT E
PE0 to PE1 PE2 to PE7
PORT F
PE7/SWP PA6/AREA
SWITCHING PULSE GENRATOR PRESCALER/ TIME BASE TIMER 6 FRC CAPTURE UNIT FIFO
PF0 to PF7
SERVO INPUT CONTROL
REEL
PORT G
PORT H
SERIAL INTERFACE UNIT RAM PROGRAMMABLE PATTERN GENERATOR
RAM
PORT I
PE1/EC
8BIT TIMER/COUNTER 0
PORT J
8BIT TIMER 1
PB0/PPO0 to PA2/PPO10
PORT K
-2-
DRUM
CAPSTAN
PG0 to PG7 PH0 to PH3 PH4 to PH7 PI0 to PI7
PG2/DREF PG3/DPG PG4/DFG PG5/CFG PG6/RFG0 PG7/RFG1 PA3/PROUT PG0/EXI0 PG1/EXI1 CS0 SI0 SO0 SCK0 PH3/CS1 PH2/SI1 PH1/SO1 PH0/SCK1
PJ0 to PJ7
PK0 to PK3 CXP87532/87540
CXP87532/87540
Pin Assignment 1 (Top View) 100pin QFP
PA3/PROUT
PA2/PPO10
PE1/INT2/EC
PA4/ATFS1
PA5/ATFS3
PA7/ATFS2
PE3/PWM1
PE4/PWM2
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO5 PB4/PPO4 PB3/PPO3 PB2/PPO2 PB1/PPO1 PB0/PPO0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE6/PWM4 PE7/SWP PK0/RFDT PK1/MCLK PK2 PK3 PG0/EXI0 PG1/EXI1 PG2/DREF PG3/DPG PG4/DFG PG5/CFG PG6/RFG0 PG7/RFG1 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 AVDD AVREF AVSS SCK0 SO0 SI0 CS0 PH0/SCK1
PJ5
PJ3
PJ0
PJ2
VSS
XTAL
PE2/PWM0
PB6/PPO6
PH3/INT1/CS1
PJ1
EXTAL
PH2/SI1
PH7
PJ7
PJ4
MP
Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to VSS.
-3-
PH1/SO1
PJ6
RST
PH6
PH5
PH4
PE5/PWM3
PB7/PPO7
PA1/PPO9
PA6/AREA
PA0/PPO8
NC
NMI
PE0/INT0
VDD
VSS
CXP87532/87540
Pin Assignment 2 (Top View) 100pin LQFP
PE1/EC/INT2
PA3/PROUT
PA2/PPO10
PA4/ATFS1
PA5/ATFS3
PA7/ATFS2
PE2/PWM0
PE3/PWM1
PE4/PWM2
PA6/AREA
PB5/PPO5
PA1/PPO9
PE5/PWM3
PA0/PPO8
PE6/PWM4
PB4/PPO4
PB6/PPO6
PB7/PPO7
VDD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PB3/PBO3 PB2/PPO2 PB1/PPO1 PB0/PPO0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PI7 PI6 PI5 PI4 PI3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VSS
PK0/RFDT
PE7/SWP
NC
NMI
PE0/INT0
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PK1/MCLK PK2 PK3 PG0/EXI0 PG1/EXI1 PG2/DREF PG3/DPG PG4/DFG PG5/CFG PG6/RFG0 PG7/RFG1 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 AVDD AVREF AVSS SCK0 SO0 SI0
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PJ1
PH3/INT1/CS1
PH0/SCK1
VSS
XTAL
PH6
EXTAL
PH7
PH5
PJ6
PJ2
PH2/SI1
PJ0
PI2
RST
Note) 1. NC (Pin 88) is always connected to VDD. 2. VSS (Pins 39 and 86) are both connected to GND. 3. MP (Pin 37) is always connected to VSS.
-4-
PH1/SO1
PH4
CS0
PJ7
PI1
PJ4
PJ5
PJ3
PI0
MP
CXP87532/87540
Pin Description Symbol PA0/PPO8 PA1/PPO9 PA2/PPO10 PA3/PROUT PA4/ATFS1 PA5/ATFS3 PA6/AREA PA7/ATFS2 PB0/PPO0 to PB7/PPO7 I/O Output/ Real time output Description (Port A) Programmable pattern generator (PPG) 8-bit output port. Output (3 pins) and capstan servo control Data is gated with PPO signal (1 pin). (3 pins), monitor signal (4 pins) in relation to ATF, control signal (1 pin) for Monitor output in relation to ATF. capstan servo by OR-gate (4 pins) and they are output. (8 pins) (Port B) Programmable pattern generator (PPG) 8-bit output port. Data is gated with PPO by OR-gate output. (8 pins) and they are output. (8 pins) (Port C) 8-bit input/output port, enables to specify input/output by 4-bit unit. (8 pins) (Port D) 8-bit input/output port. Lower 4 bits can be specified as input/output by bit unit and upper 4 bits can be specified as input/output by 4-bit unit. (8 pins) Input pin to request external interruption. Active when falling edge. (Port E) 8-bit port. Lower 2 bits are input pins and upper 6 bits are output pins. (8 pins) External event input pin for timer/counter. Input pin to request external interruption. Active when falling edge.
Output/ Monitor output
Output/ Real time output
PC0 to PC7
I/O
PD0 to PD7
I/O
PE0/INT0
Input/Input Input/Input/ Input
PE1/EC/INT2 PE2/PWM0 to PE6/PWM4 PE7/SWP PF0/AN0 to PF7/AN7 PG0/EXI0 PG1/EXI1 PG2/DREF PG3/DPG PG4/DFG PG5/CFG PG6/RFG0 PG7/RFG1
Output/Output Output/Output
PWM output pins (5 pins) SWP output pin.
Input/Input
(Port F) 8-bit input port. (8 pins) Upper 4 bits serve as standby release input pin.
Analog input pins to A/D converter. (8 pins)
Input/Input Input/Input Input/Input Input/Input Input/Input Input/Input Input/Input Input/Input (Port G) 8-bit input port. (8 pins)
External input pin 0. External input pin 1. Drum reference signal input pin. Drum PG input pin. Drum FG input pin. Capstan FG input pin. Reel FG input pin.
-5-
CXP87532/87540
Symbol PH0/SCK1 PH1/SO1 PH2/SI1 PH3/INT1/ CS1
I/O Input/I/O Input/Output Input/Input Input/Input/Input (Port H) 4-bit input port. (4 pins)
Description Serial clock input/output pin. Serial data output pin. Serial data input pin.
Input pin to request external interruption. Chip select input pin to serial interface. Active when falling edge. (Port H) 4-bit output port. N-ch open drain output of middle tension proof (12V) and large current (12mA). (4 pins) (Port I) 8-bit input/output port, enables to specify input/output by 4-bit unit. (8 pins) (Port J) 8-bit input/output port, enables to specify input/output by 4-bit unit. (8 pins) (Port K) 4-bit input/output port, enables to specify input/ output by bit unit. (4 pins) Serial clock input/output pin. Serial data output pin. Serial data input pin. Chip select input pin to serial interface. Non-maskable interrupt request pin. Active during falling edge. Connecting pin of crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and set XTAL pin to open. System reset pin of active "L" level. RST pin is input/output pin, which output "L" level by incorporated power on reset function when power ON. (Mask option) Test mode pin. This pin is always connected to GND. Positive power supply pin of A/D converter. Set the same voltage as VDD. Playback data input pin. Channel clock input pin.
PH7 to PH4
Output
PI0 to PI7
I/O
PJ0 to PJ7 PK0/RFDT PK1/MCLK PK2, PK3 SCK0 SO0 SI0 CS0 NMI EXTAL XTAL
I/O I/O/Input I/O/Input I/O I/O Output Input Input Input Input Output
RST
I/O
MP AVDD AVREF AVSS VDD VSS
Input
Input
Reference voltage input pin of A/D converter. GND pin of A/D converter. Positive power supply pin. GND pin. Connect both VSS pins to GND.
-6-
CXP87532/87540
I/O Circuit Formats for Pins Pin PA0/PPO8 to PA2/PPO10 PA3/PROUT PA4/ATFS1 PA5/ATFS3 PA6/AREA PA7/ATFS2 PB0/PPO0 to PB7/PPO7 16 pins Port A Port B
PPO, PROUT, ATFS1 to ATFS3, AREA, data
Circuit format
When reset
Port A or Port B
Hi-Z
Output becomes active from high impedance by data writing to port register.
Data bus RD
Port C
Port C data
PC0 to PC7
Port C direction (Every 4 bits) Data bus RD (Port C) IP
Input protection circuit
Hi-Z
8 pins Port D
Port D data
Buffer
PD0 to PD7
Port D direction Lower 4 bits are by bit unit and upper 4 bits are by 4bit unit RD (Port D) IP
Large current 12mA
Hi-Z
Data bus
8 pins Port E
Schmitt input
PE0/INT0 PE1/EC/ INT2
IP Data bus RD (Port E)
Hi-Z
2 pins -7-
CXP87532/87540
Pin Port E
PWM output Hi-Z control
Circuit format
When reset
MPX
PE2/PWM0 PE3/PWM1 PE4/PWM2 PE5/PWM3
Port E data
Hi-Z
Port/PWM output select Data bus RD (Port E)
4 pins Port E
PWM, SWP output MPX
PE6/PWM4 PE7/SWP
Port E data
H level
Port/PWM, SWP output select Data bus
2 pins Port F
RD (Port E)
Input multiplexer IP A/D converter
PF0/AN0 to PF7/AN7
Analog/Digial input select
Hi-Z
Data bus
8 pins Port G PG0/EXI0 PG1/EXI1 PG2/DREF PG3/DPG PG4/DFG PG5/CFG PG6/RFG0 PG7/RFG1 8 pins
Schmitt input IP
RD (Port F)
Servo input Data bus RD (Port G)
Hi-Z
For PG0/EXI0 to PG7/RFG1, TTL schmitt input can be selected with the mask option.
-8-
CXP87532/87540
Pin Port H
Internal serial clock from SI0
Circuit format
When reset
SCK1 output enable
IP
PH0/SCK1
Schmitt input External serial clock to SI0 Data bus RD (Port H)
Hi-Z
1 pin Port H
SO1 from SI0
PH1/SO1
SO1 output enable IP
Hi-Z
Data bus RD (Port H)
1 pin Port H
Schmitt input
PH2/SI1 PH3/CS1/ INT1
IP
Hi-Z
Data bus RD (Port H)
2 pins Port H
Middle tension proof 12V
PH4 to PH7
Port H data Large current 12mA Data bus RD (Port H)
Open
4 pins
-9-
CXP87532/87540
Pin Port I
Circuit format
When reset
Port I data
PI0 to PI7
Port I direction (Every 4 bits) Data bus RD (Port I)
IP
Input protection circuit
Hi-Z
8 pins Port J
Buffer
Port J data
PJ0 to PJ7
Port J direction (Every 4 bits) Data bus RD (Port J) IP
Hi-Z
8 pins Port K Hi-Z
Port K data
PK0/RFDT
Port K direction (Every bit) Data bus Servo input Buffer amplifier input can be selected with the mask option. RD (Port K) IP Input protection circuit
When buffer amplifier input is selected, pulled up internally during standby.
1 pin
- 10 -
CXP87532/87540
Pin Port K
Port K data
Circuit format
When reset
PK1/MCLK
Port K direction (Every bit) Data bus RD (Port K)
IP
Input protection circuit
Hi-Z
Servo input
1 pin Port K
TTL schmitt input can be selected with the mask option.
Port K data
PK2 to PK3
Port K direction (Every bit) Data bus RD (Port K) IP
Hi-Z
2 pins
CS0 SI0
Schmitt input IP To SI0
Hi-Z
2 pins
SO0
SO0 from SI0
Hi-Z
SO0 output enable
1 pin
Internal serial clock from SI0
SCK0
SCK0 output enable External serial clock to SI0 IP
Hi-Z
1 pin - 11 -
Schmitt input
CXP87532/87540
Pin
Circuit format
When reset
EXTAL XTAL
EXTAL
IP
* Shows the circuit composition during oscillation. * Feedback resistor is removed during stop.
Oscillation
XTAL
2 pins
Pull-up resistor
Mask option
RST
OP
Schmitt input
L level
From power on reset circuit (Mask option)
1 pin
Schmitt input
NMI
IP Interruption circuit
Hi-Z
1 pin
- 12 -
CXP87532/87540
Absolute Maximum Ratings Item Symbol VDD Power supply voltage Input voltage Output voltage Middle tension proof output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation AVDD AVSS VIN VOUT VOUTP IOH IOH IOL IOLC IOL Topr Tstg PD Ratings -0.3 to +7.0 AVSS to +7.01 -0.3 to +0.3 -0.3 to +7.02 -0.3 to +7.02 -0.3 to +15.0 -5 -50 15 20 130 -20 to +75 -55 to +150 600 380 mW Unit V V V V V mA mA mA mA mA mA C C QFP package LQFP package PH pin
(VSS = 0V reference) Remarks
Total of entire output pins Other than large current output pins : per pin Large current port pin 3 : per pin Total of entire output pins
1 AVDD and VDD should be set to the same voltage. 2 VIN and VOUT should not exceed VDD + 0.3V 3 The large current operation transistors are the N-ch transistors of the PD and PH4 to PH7. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI.
- 13 -
CXP87532/87540
Recommended Operating Conditions Item Power supply voltage Analog voltage Symbol VDD AVDD VIH High level input voltage VIHS VIHTS VIHEX VIL Low level input voltage VILS VILTS VILEX Operating temperature Topr Min. 4.5 2.5 4.5 0.7VDD 0.8VDD 2.2 Max. 5.5 5.5 5.5 VDD VDD VDD V V V V V V V V V V C Unit
(VSS = 0V reference) Remarks Guaranteed range during operation Guaranteed data hold operation range during STOP 1 2 CMOS schmitt input 3 TTL schmitt input 4 EXTAL pin 5 2 CMOS schmitt input 3 TTL schmitt input 4 EXTAL pin 5
VDD - 0.4 VDD + 0.3 0 0 0 -0.3 -20 0.3VDD 0.2VDD 0.8 0.4 +75
1 AVDD and VDD should be set to the same voltage. 2 Normal input port (Each pin of PC, PD, PF and PH1). 3 Each pin of NMI, CS0, SI0, SCK0, RST, PE0/INT0, PE1/EC/INT2, PH0/SCK1, PH2/SI1, PH3/INT1/CS1, PG and PK1/MCLK (when CMOS schmitt input is selected with mask option for PG, PK1/MCLK). 4 Each pin of PG and PK1/MCLK (when TTL schmitt input is selected with mask option). 5 Specified only during external clock input.
- 14 -
CXP87532/87540
DC Characteristics Item High level output voltage Low level output voltage Symbol VOH Pin
PA to PD, PE2 to PE7, PH0, PH1, SO0, SCK0 PH4 to PH7 (VOL only) RST1 (VOL only) PI to PK
(Ta = -20 to +75C, VSS = 0V reference) Condition VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V EXTAL RST2 PA to PG PH0 to PH3, CS0, SI0, SO0, SCK0, NMI, RST2 PI to PK3 VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V 0.5 -0.5 -1.5 Min. 4.0 3.5 0.4 0.6 1.5 40 -40 -400 Typ. Max. Unit V V V V V A A A
VOL
PD, PH4 to PH7 IIHE Input current IILE IILR
I/O leakage current
IIZ
VDD = 5.5V VI = 0, 5.5V
10
A
Open drain output leakage current (N-ch Tr OFF in state)
ILOH
PH4 to PH7
VDD = 5.5V VOH = 12V
50
A
Current power supply
IDD VDD
Operating mode (1/2 dividing clock) 12.288MHz crystal oscillation (C1 = C2 = 12pF) Entire output pins open Sleep mode Stop mode
20
45
mA
IDDSL IDDST Input capacity CIN Other than VDD, VSS, AVDD, and AVSS pins
5
17 10
mA A pF
Clock 1MHz 0V other than the measured pins
10
20
1 RST pin specifies only when the power on reset circuit is selected with mask option. 2 RST pin specifies the input current when the pull-up resistance is selected, and specifies leakage current when non-resistance is selected. 3 PK0 pin specifies only when the normal input circuit is selected with mask option.
- 15 -
CXP87532/87540
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rising and falling times Event count input clock pulse width Event count input clock rising and falling times 1 Symbol fC Pin XTAL EXTAL EXTAL EXTAL EC EC
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, VSS = 0V reference) Condition Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 Min. 1 36 200 Max. 12.288 Unit MHz ns ns ns 20 ms
tXL, tXH tCR, tCF tEH, tEL tER, tEF
tsys + 501
tsys indicates three values according to the contents of the clock control register (address : 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL 0.4V
tXH
tCF
tXL
tCR
Fig. 2. Clock applying condition
Crystal oscillation Ceramic oscillation External clock
EXTAL
XTAL
EXTAL
XTAL 74HCO4
C1
C2
Fig. 3. Event count clock timing
0.8VDD EC 0.2VDD
tEH
tEF
tEL
tER
- 16 -
CXP87532/87540
(2) Serial transfer Item CS SCK delay time CS SCK floating delay time CS SO delay time CS SO floating delay time CS high level width SCK cycle time SCK high and low level widths SI input setup time (against SCK ) SI input hold time (against SCK ) SCK SO delay time Note 1) Symbol Pin SCK0, SCK1 SCK0, SCK1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, VSS = 0V reference) Condition Chip select transfer mode (SCK = Output mode) Chip select transfer mode (SCK = Output mode) Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 200 100 ns ns
tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 8000/fc
SO0, SO1 Chip select transfer mode SO0, SO1 Chip select transfer mode CS0, CS1 Chip select transfer mode SCK0, SCK1 SCK0, SCK1 SI0, SI1 Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SI0, SI1 SCK output mode SCK input mode SO0, SO1 SCK output mode
tsys + 100
4000/fc - 50 -tsys + 100 200 2tsys + 100 100
tsys indicates three values according to the contents of the clock control register (address : 00FEH)
upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The marks CS, SCK, SI and SO respectivery mean pins of CS CS0, CS1, SCK SCK0, SCK1, SI SI0, SI1 and SO SO0, SO1. Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
- 17 -
CXP87532/87540
Fig. 4. Serial transfer timing
tWHCS
CS0 CS1
0.8VDD
0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 SCK1 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 SI1 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 SO1 Output data 0.2VDD
- 18 -
CXP87532/87540
(3) A/D converter characteristics (Ta = -20 to +75C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, VSS = AVSS = 0V reference) Item Resolution Linearity error Zero transition voltage Full scale transition voltage Conversion time Sampling time Reference input voltage Analog input voltage AVREF current VZT1 VFT2 Ta = 25C VDD = AVDD = 5.0V VSS = AVSS = 0V -10 4930 160/fC 12/fC AVREF AN0 to AN7 Operating mode AVREF Sleep mode Stop mode AVDD - 0.5 0 0.6 AVDD AVREF 1.0 10 30 4970 Symbol Pin Condition Min. Typ. Max. 8 1 70 5010 Unit bits LSB mV mV s s V V mA A
tCONV tSAMP
VREF VIAN IREF IREFS
Fig. 5. Definitions of A/D converter terms
FFH FEH
Digital conversion value
Linearity error 01H 00H VZT Analog input VFT
1 VZT : Indicates the value that digital conversion value changes from 00H to 01H and vice versa. 2 VFT : Indicates the value that digital conversion value changes from FEH to FFH and vice versa.
- 19 -
CXP87532/87540
(4) Interruption, reset input Item External interruption high and low level widths Reset input low level width Fig. 6. Interruption input timing
INT0 INT1 INT2 NMI (Falling edge)
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, VSS = 0V reference) Symbol Pin INT0 INT1 INT2 NMI RST Condition Min. Max. Unit
tIH tIL tRSL
1
s
8/fc
s
tIH
tIL
0.8VDD 0.2VDD
Fig. 7. RST input timing
tRSL
RST 0.2VDD
(5) Power on reset Power on reset Item Power supply rising time Power supply cut-off time Symbol
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, VSS = 0V reference) Pin Condition Power on reset VDD Repetitive power on reset Min. 0.05 1 Max. 50 Unit ms ms
tR tOFF
Specifies only when power on reset function is selected. Fig. 8. Power on reset
4.5V VDD 0.2V tOFF 0.2V
tR The power supply should rise smoothly.
- 20 -
CXP87532/87540
(6) Others Item RFDT input high and low level widths MCLK input high and low level widths DREF input high and low level widths DPG input high and low level widths DFG input high and low level widths CFG input high and low level widths RFG input high and low level widths EXI input high and low level widths 1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, VSS = 0V reference) Symbol Pin RFDT MCLK DREF DPG DFG CFG RFG0 RFG1 EXI0 EXI1 Condition Min. 2.5tMCK1 326/fc Max. Unit ns ns ns ns ns ns ns ns
tRDH tRDL tMCH tMCL tDRH tDRL tDPH tDPL tDFH tDFL tCFH tCFL tRFH tRFL tEIH tEIL
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys = 2000/fc tsys + 200
tMCK indicates three values according to the contents of the ATF control register (address : 01EEH) bits 5
and 4 (MCLK input control). tMCK [ns] = tMCH or tMCL (bits 5 and 4 = "00"), 2tMCH or 2tMCL (bits 5 and 4 = "01"), 4tMCH or 4tMCL (bits 5 and 4 = "10").
- 21 -
CXP87532/87540
Fig. 9. Other timing
tRDH tRDL
RFDT
tMCH
tMCL
MCLK
tDRH
tDRL
DREF
tDPH
tDPL
DPG
tDFH
tDFL
DFG
tCFH
tCFL
CFG
tRFH
tRFL
RFG0 RFG1
tEIH
tEIL
EXI0 EXI1
- 22 -
CXP87532/87540
(7) Buffer amplifier function Item Buffer amplifier input voltage1 (Peak to peak value) Symbol VAPP
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, VSS = 0V reference) Pin RFDT Condition When inputting 400kHz sine wave on Fig. 10 circuit. Min. 2.0 Max. VDD + 0.3 Unit V
1 When buffer amplifier input circuit format of RFDT pin is selected with option.
Fig. 10.
VAPP (Refer to Fig. 11.) C
VDD RFDT C: 4700pF (5%)
VSS
Note) VAPP waveform indicates the range like Fig. 11. When composed by circuits other than Fig. 10. (when DC bias does not become VDD/2), it should not exceed VDD + 0.3 (V) and -0.3 (V) (VSS = 0V).
Fig. 11.
VAPP VDD/2
- 23 -
CXP87532/87540
Supplement Fig. 12. SPC700 series recommended oscillation circuit Manufacturer
EXTAL XTAL
Model
Frequency f (MHz) 6.00
C1, C2 (pF) 12 12 10
C1
C2
RIVER ELETEC CORPORATION
HC-49/U-03
8.00 12.000
Mask option table Item Reset pin pull-up resistor Power on reset circuit Input circuit format1 Contents Non-existent Non-existent CMOS Schmitt Buffer amplifier Existent Existent TTL Schmitt Normal input
1 On PG0/EXI0 pin to PG7/RFG1 pin and PK1/MCLK pin, the input circuit format of CMOS schmitt or TTL schmitt can be selected to every pin. On PK0/RFDT pin, buffer amplifier or normal input circuit format can be selected.
- 24 -
CXP87532/87540
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 80 51 + 0.1 0.15 - 0.05
81
50
+ 0.4 14.0 - 0.1 17.9 0.4
15.8 0.4
A 100 31
1
0.65
+ 0.15 0.3 - 0.1
30 0.13 M + 0.35 2.75 - 0.15
+ 0.2 0.1 - 0.05
0.15
DETAIL A
0.8 0.2
0 to 10
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g
100PIN LQFP (PLASTIC)
16.0 0.2 75 76 14.0 0.1 51 50
100 1 0.5 + 0.08 0.18 - 0.03 25
26 (0.22)
0.13 M
+ 0.2 1.5 - 0.1
+ 0.05 0.127 - 0.02 0.1
0.1 0.1
0 to 10
DETAIL A
0.5 0.2
NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42 ALLOY 0.8g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
SONY CODE EIAJ CODE JEDEC CODE
LQFP-100P-L01 LQFP100-P-1414
- 25 -
0.5 0.2
A
(15.0)

▲Up To Search▲

Price & Availability of CXP87532

	To Download CXP87532 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .